1. Field of the Invention
The present invention relates to a data processing system, and more particularly to a data processing system for dividing an inner part into a plurality of processing blocks and controlling the processing blocks self-synchronously.
2. Description of the Background Art
A data processing system basically carries out control synchronously with a single system clock. In an apparatus for dividing the data processing system into a plurality of processing blocks to execute a whole processing, it is necessary to control a clock skew to have a specific reference value or less for a clock to be a synchronizing signal in the processing blocks and between the processing blocks.
In recent years, a physical control area has been enlarged with an increase in an operation speed and a scale of a system so that the reference value for the clock skew has been decreased. Thus, a situation has become increasingly tense and the clock skew having the reference value or less has been hard to implement.
Therefore, various methods for implementing the clock skew having the reference value or less have been described in Brian Curran et al., ISSCC 2001 Proceeding 15.5 “A1.1 GHz First 64 b Generation Z900 Microprocessor” p. 238-239, 454 (which will be hereinafter referred to as Document 1), Hidehiro TAKATA et al., IEICE on Electronics “Physical Design Methodology for On-Chip 64-Mb DRAM MPEG-2 Encoding with a Multimedia Processor) VOL. E85-C No. 2 February 2002 p. 368-374 (which will be hereinafter referred to as Document 2), Kouichi Yamaguchi et al., ISSCC 2001 Proceeding 25.4 “2.5 GHz 4-phase Clock Generator with Scalable and No Feedback Loop Architecture” p. 398-399, 326-327 (which will be hereinafter referred to as Document 3), and Thucydides Xanthopoulos et al., ISSCC 2001 Proceeding 25.6 “The Design and Analysis of the Clock Distribution Network for a 1.2 GHz Alpha Microprocessor” p. 402-403, 330-331 (which will be hereinafter referred to as Document 4).
More specifically, the Document 1 has described a method of employing a tree structure having an equal-length wiring for a clock line to be supplied to each processing block and carrying out a management for causing delay values sent from a clock generating source to each processing block to be equal to each other.
Moreover, the Document 2 has described a method of hierarchically carrying out a management based on a clock management on a block level in which a clock management area is restricted to a local area and a clock management between these blocks and adjusting a delay value by a delay adjusting circuit provided in a clock generating source in the clock management between the blocks.
The Documents 3 and 4 have described a method using a DLL (Delay Locked Loop) circuit for adjusting a clock phase between blocks in a method of hierarchically carrying out a clock management on a block level between blocks.
In these methods, the clock management is carried out in a two-stage hierarchy including an in-block (lower level) management and an interblock (an upper level) management in which an area is restricted, and “a tree structure having an equal-length wiring”, “a delay value adjustment to be carried out by a delay adjusting circuit”, “a clock phase adjustment to be carried out by a DLL” and the like are given to a clock management having an upper level which is harder to perform.
In the case in which supply of a clock or a power is to be stopped in order to reduce power consumption for a specific processing block, moreover, a control signal to satisfy supply stop conditions for the clock or the power is generated and the supply of the clock or the power is turned ON/OFF in response to the control signal.
As described above, in the apparatus for controlling a system synchronously with a single clock, a method of hierarchically managing a clock skew at a lower level on a block unit and an upper level between blocks has conventionally been used for a method of setting a clock skew to have a predetermined reference value or less.
While a management of a phase difference in a clock at a lower level can be implemented comparatively easily by reducing an area, a management of a phase difference in a clock at an upper level is harder to perform because an area to be managed covers a wide range. For this reason, there have been employed the techniques such as “a tree structure having an equal-length wiring”, “a delay value adjustment to be carried out by a delay adjusting circuit”, “a clock phase adjustment to be carried out by a DLL” and the like.
These techniques are to optimize a clock path to be distributed to each block and a great deal of labor is required for a design, a verification and an analysis.
Referring to “a delay value adjustment to be carried out by a delay adjusting circuit” and “a clock phase adjustment to be carried out by a DLL”, furthermore, a delay adjusting circuit, a DLL and the like are required. Consequently, scales of the circuits are increased, and furthermore, these circuits are to be tuned up. Thus, a design period is increased.
In the case in which the supply of the clock or the power is to be stopped in order to reduce the power consumption for a specific processing block, moreover, it is necessary to generate a control signal to satisfy the supply stop conditions of the clock or the power.